1. Field of the Invention
The present invention relates generally to non-volatile semiconductor memory devices such as flash memory chips of the NAND type, and more particularly to sub-block erase methodology for use therewith.
2. Description of the Related Art
NAND-type flash memory chips are widely used as file storage memories, which in turn are for use as recording media of music data and image data. As the music data and image data are larger in file size, NAND flash memories also increase in storage capacity, resulting in a likewise increase in storage capacity of a unitary portion for a write (page) and an erase unit (block) of NAND flash memories. Generally one block of NAND flash memory is an ensemble of multiple pages so that the block capacity becomes several times greater than the capacity of a page. As the block capacity becomes larger in the way stated above, the resultant efficiency becomes inferior in the case of erasing or rewriting a small capacity of data.
To avoid this problem, an operation scheme for erasing only part of the block capacity (sub-block erase) has been proposed (U.S. Pat. No. 5,293,337 and U.S. Pat. No. 5,402,373). This sub-block erase is a scheme for erasing a portion of the block capacity in units of page capacities and thus is a scheme for efficiently erasing or rewriting a small amount of data.
An explanation will be given of a block erase operation, sub-block erase operation, and write operation of a NAND flash memory below.
FIG. 11 shows an extracted portion of a memory cell array of NAND flash memory chip. The memory cell array has a plurality of cell array blocks BLK and BLK′, and each block BLK, BLK′ includes a plurality of NAND cell units NU, which correspond in number to bit lines BL0, BL1, . . . , BLj. One NAND cell unit NU in the NAND flash memory is made up of two select gate transistors S1 and S2, and memory cells MC0 to MCi which are connected in series between these select gate transistors S1, S2. A source of the select gate transistor S1 is connected to a source line CELSRC, while a drain of the select gate transistor S2 is connected to a corresponding one of the bit lines BL0 to BLj. Select gates of the select gate transistors S1, S2 and control gates of memory cells MC0-MCi are commonly connected in a row direction by select gate lines SGS, SGD and word lines WL0 to WLi, respectively.
Note here that a unitary portion for write—say, write unit—of the memory cell array is an ensemble (page) of memory cells MC which are queued in a column direction while these are connected together to a single word line WL. In contrast, an erase unit is as follows: in the case of prior known block erase, the erase unit is an ensemble EU of all the memory cells MC within a cell array block BLK; in the case of sub-block erase, an erase operation is done on a per-page basis in a similar way to the write unit.
FIGS. 12A and 12B show cross-sectional views of one memory cell MC of the NAND flash memory, and FIG. 12C is a threshold voltage distribution pattern thereof. As shown in FIG. 12A, in the case of erasing data of the memory cell MC, let a control gate (word line) 510 be applied to ground, and potentially raise or “boost” a well region 513 of the cell up to an erase voltage (e.g. 20V). Whereby, a junction of source/drain 512 becomes forward-biased and thus boosted so that a high electric field is applied between a floating gate 511 for use as a carrier storage layer and the cell's well 513, causing electrons to be drawn out of the floating gate 511. This results in a decrease in threshold voltage of the memory cell.
On the other hand, an operation for writing data into the memory cell MC is as follows. As shown in FIG. 12B, apply the cell's well 513 and source/drain 512 to ground, and potentially boost the control gate 510 to a write voltage (e.g. 20V). Apply an intermediate voltage (10V) to the control gates of all the other memory cells which are series-connected to this memory cell, and give a data voltage of 0V to a bit line associated therewith. With such voltage application, a channel is formed between the source and drain of the memory cell, and a high electric field is applied between the floating gate 511 and the channel, causing electrons within the channel to be injected onto floating gate 511. A result of this electron injection is that the memory cell increases in threshold voltage.
FIG. 12C shows a typical threshold voltage distribution of the memory cell. Suppose that a state with data being written into the memory cell is a logic “0” data, whereas an erased state is a logic “1” data. An erased cell is in the state that its threshold voltage Vth is negative whereas a written or “programmed” cell is such that its threshold voltage Vth is positive and is greater than or equal to Vv0 and yet less than a read voltage Vread.
Here, when erasing by conventional block erase techniques the data of those memory cells of the cell array shown in FIG. 11 which are connected to word lines WL0-WL3, an operation will be performed in a routine which follows.
(1) In the block BLK, read data of a memory cell MC4 that is connected to a word line WL4 and then transfer and save the read data to a memory cell MC4′ of another block BLK′, which cell is connected to the word line WL4.
(2) Regarding memory cells MC5 to MCi of the block BLK which are connected to word lines WL5-WLi, perform data transfer/saving to the block BLK′ in a way similar to the step (1).
(3) Erase the block BLK.
When rewriting or “re-programming” the data of the memory cells MC0-MC3, first perform the operation at the step (1) to (3) and thereafter write data bits into memory cells MC0-MC3, respectively.
Note here that in the case of a NAND flash memory with its block capacity of 128 kilobytes (kB) and page capacity of 2 kB, a NAND cell unit NU is such that thirty two (32) memory cells MC0-MC31 are series-connected. Accordingly, in the case of performing the above-noted steps (1) to (3), the intended operation is completed only after the read operation is recurrently performed for twenty eight (28) times and the write is repeated 28 times at the steps (1) and (2) and then the erase is done for one time. This approach must be low in efficiency.
Alternatively, using a sub-block erase technique makes it possible to perform the required operation for erasing data of the memory cells MC0-MC3 as connected to the word lines WL0-WL3 in a way which follows.
(1) Erase the data of memory cells MC0-MC3 that are connected to the word lines WL0-WL3 (i.e., sub-block erase).
In other words, the intended operation is completed by mere execution of a single step of erase operation.
When rewriting the data of memory cells MC0-MC3, first perform the step (1), and thereafter write data bits into the memory cells MC0-MC3, respectively.
As stated above, use of the sub-block erase technique makes it possible to easily achieve erase and rewrite of small-capacity data.
As apparent from the foregoing, whereas the block erase operation is inherently designed to erase data of all the memory cells within a NAND cell unit at a time in a way known as the “all-at-once” erase, the sub-block erase scheme enables only the data of a selected memory cell or cells which is/are part of such NAND cell unit while permitting data of the remaining memory cells to be retained with no changes. However, in the case of the sub-block erase, it becomes possible to repeat again and again the execution of erase and data write with respect to any given cell of the NAND cell unit, almost unlimitedly in execution number. In other words, any limitation disappears in the erase execution number and data write execution number in a given block. Due to this, in cases where erase/write is recurrently performed only with respect to a specific page within a presently selected block, the intermediate voltage (10V) must be iteratively applied to the control gates in those pages other than a specified page within such selected block. This would cause the threshold voltage of the pages that are not to be rewritten to gradually shift or offset toward the positive potential direction, resulting in the risk of unwanted occurrence of over-programmed cells.
More specifically, assuming that data has already been written into the memory cell MC0 of FIG. 11, in the case of prior art block erase schemes, the number of times that the intermediate voltage (10V) is applied to the gate of memory cell MC0 is equal to the number of times that data is written into all the other memory cells MC1-MCi within the block. In contrast, in the case of using the sub-block erase method, data erase and write on a per-sub-block basis are still possible even after all the memory cells MC0-MCi have been written data; thus, the number of times that the intermediate voltage is applied to the gate of any given cell is equal to a total sum of the number of times in the case of block erase and the number of times that sub-block erased memory cells are written or “programmed.” In case specific setting is made to enable the sub-block erase to be repeated without any limitation in execution number, the time period for application of the intermediate voltage becomes almost unlimited.
As the total sum of time periods for applying the intermediate voltage to the control gates of those memory cells that are not to be written becomes longer, the memory cells become higher in threshold voltage Vth accordingly; thus, if the memory cell of interest is an erased cell (“1” data cell) then this cell can change to a “0” data cell in some cases, although the possibility of such state change or transition stays extremely low. If this is the case, an error correcting circuit external to the flash memory chip is employable to perform decoding. Unfortunately it may be contemplated that if the memory cell is a data written cell (“0” data cell) then this cell's threshold voltage Vth gets higher in potential than the read voltage Vread shown in FIG. 12C, although the possibility is extremely low. When the threshold voltage Vth of such memory cell becomes higher than the read voltage Vread, it is no longer possible to read data out of every memory cell of the NAND cell unit to which such memory cell belongs.
Consequently, in the event that a sub-block erase verify read session is ended with a result of failure to complete the intended erase successfully, two reasons for explanation of such result are considered: one reason is that the cell being erased fails to be fully erased; the other is that within the NAND cell unit to which the erased cell belongs, more than one cell with its threshold voltage Vth higher than Vread (i.e. over-programmed cell) must be present in those cells that are not to be erased. However, with the prior art verify read and sub-block verify read schemes, even when the result that the erase is not completed yet is obtained, it is still impossible to determine this result is due to which one of the two causes. Thus the resulting sub-block erase time period (erase loop execution number) becomes longer, which requires extra application of the erase voltage high in potential to the NAND flash memory. This would result in the to-be-erased cell being erased excessively or “over-erased,” which in turn leads to the risk that the cell's threshold voltage distribution becomes wider undesirably.